Conventionally, in a layer 2 (L2) switch, address learning for registering a source address (SA) in a forwarding database (FDB) is performed by switch hardware. FIG. 1 is a diagram illustrating an example of related art. As illustrated in FIG. 1, a switch large scale integrated circuit (LSI) 10, which is switch hardware, includes ports 12, an FDB 14, and a manager 16.
In operation S1001, the switch LSI 10 searches the FDB 14 by a source address (SA) of a packet received via the ports 12.
In operation S1002, the switch LSI 10 transmits a search result to the manager 16.
In operation S1003, when the SA has not been registered in the FDB 14, the manager 16 registers the SA in the FDB 14.
The manager included in such a switch LSI may only perform simple registration of an SA, and may not be able to handle a case in which filtering by a sophisticated process such as authentication is required. The case in which filtering by a sophisticated process is required includes a case in which a virtual local area network (VLAN) of a received packet is at variance with a VLAN identifier (ID) of an address to be registered, a case in which a plurality of entries having different VLAN IDs are required for registering an SA of a received packet, and a case in which an address conversion is required for a port of different domain.
A technique for performing address learning in such hardware includes a technique in which time necessary for packet transfer is determined on the basis of a length of a packet, actual time for determining a transfer destination is measured, and whether an additional process such as media access control (MAC) address learning should be performed or not is determined in accordance with a time difference between the time necessary for packet transfer and the actual time for determining a transfer destination. In this way, packet losses may decrease, and a system of lower cost and higher cost performance may be constituted, comparing with a case in which an additional process such as MAC address learning is performed for every packet. Furthermore, in that technique, address learning is not concentrated on specific addresses, but the address learning is efficiently performed.